Electronic devices are becoming more and more tiny each generation because of transistors shrinking. The scaling of transistors from the micro-scale to the nano-scale brings its own set of challenges. Let us use Silvaco to find out what goes on under the package.
MOSFET Structure
Structure processing was done by Athena. Gate oxide was grown and the undesirable areas were etched out, then ion implantation was used to dope the drain and source regions. Annealling and gate metal deposition was initiated and finally a silicon nitride spacer was created beside the gate.
Why are scaling parameters necessary?
As transistors get smaller, it enables increased transistor density, higher switching performance, and miniaturization of electronic components. Shrinking channel lengths give rise to it’s own host of problems like drain induced barrier lowering and punch through of depletion region which lowers threshold voltage and reduces gate control. To address these issues while preserving device performance, various scaling methodologies have been proposed over the years. These scaling approaches define how critical device parameters such as channel length, oxide thickness, junction depth, supply voltage, and doping concentration should be modified as device dimensions are reduced. These were:
Dennard Scaling (Constant Field Scaling)
It was proposed in 1974 by Robert H. Dennard and his colleagues at IBM in the landmark paper “Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions.” The fundamental concept of Dennard Scaling is that as transistor dimensions are reduced by a scaling factor S, all voltages must also be reduced by the same factor. By scaling both dimensions and voltages proportionally, the internal electric field remains constant, allowing device performance to improve without compromising reliability.
Electric field inside a MOSFET is approximated as:
where E is electric field, V is applied voltage, and L is the channel length.
If both voltage and channel length are scaled by the same factor S,
then
Thus, the electric field remains unchanged.
Table 1: Dennard scaling summary table
| Parameter | Scaling Rule |
| Channel Length L | L/S |
| Channel Width W | W/S |
| Oxide Thickness tox | tox /S |
| Junction Depth xj | xj /S |
| Supply Voltage VDD | VDD /S |
| Threshold Voltage VT | VT /S |
| Doping Concentration N | N*S |
| Electric Field E | E |
| Gate Capacitance Cg | Cg /S |
| Switching Delay τ | τ/S |
| Power per Device P | P/S2 |
It gave a foundation for modern transistor miniaturization by demonstrating that simultaneous scaling of dimensions, voltages, and doping concentration could maintain a constant electric field while improving device density and speed.
Constant Voltage Scaling
It emerged as an alternative theoretical scaling methodology during the late 1970s and early 1980s in which transistor dimensions are reduced while operating voltage remains unchanged. Unlike Dennard scaling, it is not associated with a single publication but is discussed in VLSI scaling literature as a reference scaling model for analyzing the effects of dimension reduction without voltage scaling.
Table 2: Constant voltage scaling summary table
| Parameter | Scaling Rule |
| Channel Length L | L/S |
| Channel Width W | W/S |
| Oxide Thickness tox | tox /S |
| Junction Depth xj | xj /S |
| Supply Voltage VDD | VDD |
| Threshold Voltage VT | VT |
| Doping Concentration N | N*S |
| Electric Field E | E*S |
| Gate Capacitance Cg | Cg /S |
| Drain Current ID | ID /S |
| Switching Delay τ | τ/S2 |
| Power per Device P | P/S |
It faced limitations due to the sharp increase in electric field causing earlier breakdown of devices, hot carrier injection, gate oxide degradation and the like. It is generally regarded as a useful theoretical scaling model rather than a practical long-term scaling strategy, showcasing the importance of voltage reduction in semiconductor scaling techniques.
De Mari Scaling
It is also recognized as ‘generalized scaling’. The concept was first introduced in A. De Mari, “An Accurate Numerical Steady-State One-Dimensional Solution of the p-n Junction,” 1968 and subsequent scaling-related work during the mid-1970s that contributed to generalized MOSFET scaling analysis. The approach was introduced to give a more realistic scaling idea which can be used in practical fabrication. It recognizes that voltage, geometry, and doping concentration cannot always be scaled proportionally in real semiconductor technologies.
Instead of a single scaling factor S, two independent scaling factors are introduced:
Device dimension scaling became:
while voltage was scaled as:
Electric field was writen as:
The primary motivation behind generalized scaling was to overcome the restrictions of Dennard scaling. It allows device engineers to have greater flexibility in device optimization by investigating how each change in parameter would affect device performance. As semiconductor technology evolved, this flexibility became increasingly important.
The two scaling methods detailed before can be considered special cases of generalized scaling.
Constant Field Scaling: α = β
Constant Voltage Scaling: β = 1
Table 3: De Mari scaling summary table
| Parameter | Scaling Rule |
| Channel Length L | L/α |
| Channel Width W | W/α |
| Oxide Thickness tox | tox /α |
| Junction Depth xj | xj /α |
| Supply Voltage VDD | VDD /β |
| Threshold Voltage VT | VT /β |
| Doping Concentration N | Independent |
| Electric Field E | (α/β)E |
| Gate Capacitance Cg | Cg /α |
| Drain Current ID | ID (α/β2) |
| Switching Delay τ | τ (β/α2) |
| Power per Device P | P (α/β3) |
Short Channel Effects
These effects cause the gate to gradually lose electrostatic control over the channel, allowing the source and drain electric fields to significantly influence carrier transport. These effects are the biggest hurdle to the miniaturization of planar MOSFETs.
Drain Induced Barrier Lowering (DIBL)
It is a phenomenon observed in MOSFETs where an increase in drain voltage reduces the potential barrier between the source and channel. As a result, carriers can enter the channel more easily, causing the threshold voltage of the device to decrease.
In long-channel MOSFETs, the gate controls the channel potential almost exclusively but, as channel length decreases, the drain electric field extends further into the channel and begins to influence the source-channel barrier. This additional drain control weakens the gate’s electrostatic control, leading to DIBL. Higher channel doping is one technique used to reduce DIBL but short channels will experience large DIBL regardless.
Threshold Voltage Roll-off
The threshold voltage (VT) decreases as the channel length is reduced. In long-channel devices, the threshold voltage is primarily determined by the gate oxide, substrate doping, and gate material. However, as the channel length approaches the depletion widths of the source and drain junctions, the gate gradually loses exclusive electrostatic control over the channel. Consequently, a smaller gate voltage is required to form the inversion layer, resulting in a reduction in threshold voltage.
MOSFETs with longer channels have the source and drain depletion regions well separated. The gate electric field solely controls the formation of the inversion channel, making the threshold voltage nearly independent of channel length. As the channel length decreases, the depletion regions associated with the source and drain extend further into the channel. Part of the channel depletion charge is shared by the source and drain instead of being controlled entirely by the gate. This phenomenon is known as charge sharing. The gate is responsible for controlling a smaller amount of depletion charge, less gate voltage is required to invert the channel, causing the threshold voltage to decrease.
Punch-through
It is also known as reach-through and it occurs when the depletion regions of the source and drain junctions expand sufficiently to merge within the channel. When this occurs, the gate loses control over the channel potential, allowing current to flow directly from the source to the drain even when the gate voltage is below the threshold voltage.
Decreasing the channel length causes the source and drain depletion regions extend further into the channel hence, the neutral channel region becomes progressively shorter. At sufficiently short channel lengths or high drain voltages, the depletion regions merge. Once the depletion regions overlap, a conductive path forms between the source and drain, allowing carriers to travel through the depleted channel regardless of the gate voltage.
Sub-threshold Leakage Current
It is the drain current that flows when the gate-to-source voltage (VGS) is below the VT. Although an ideal MOSFET is expected to remain completely OFF under this condition, a small current continues to flow due to the diffusion of minority carriers through the weakly inverted channel.
In the OFF state, the channel is not strongly inverted. However, the gate voltage is still sufficient to induce a weak inversion layer near the semiconductor surface. Unlike the ON-state current, which is dominated by carrier drift under the influence of an electric field, subthreshold current is primarily caused by the diffusion of carriers from the source to the drain due to the concentration gradient along the weak inversion channel. As the gate voltage approaches the threshold voltage, the carrier concentration in the channel increases exponentially, causing the drain current to increase exponentially.
Electrical Characterization
Transfer and output characteristics of the simulated MOSFETs will be discussed in this section.
Figure 6 shows the continued increase in drain current due to the lowering of channel length. At the lowest channel length of 62.5 nm, it shows depletion mode characteristics as the threshold voltage is below zero volts. Sub-threshold leakage current increases with lowering channel length.
Lowering channel and increasing doping without proper optimization causes very low electrostatic control by the gate which allows almost resistor-like characteristics in MOSFETs. DIBL and punch-through are the biggest effects hampering MOSFET performance.
Conclusion
Aggressive geometric scaling without maintaining appropriate electrostatic scaling results in a progressive loss of gate control. As the channel length becomes comparable to the depletion widths of the source and drain junctions, short-channel effects dominate device operation. As a consequence, the MOSFET gradually loses its switching characteristics and exhibits resistor-like behavior, characterized by high OFF-state current, poor current saturation, and weak dependence on gate voltage.
Source Code: Arjun’s GitHub
Frequently Asked Questions (FAQ)
Ques: Why is electric field kept constant while scaling down MOSFETs?
As MOSFET dimensions are reduced, the electric field inside the device tends to increase if the operating voltage remains unchanged. Excessively high electric fields can lead to reliability issues such as hot-carrier injection, oxide breakdown, and increased power density. To counter this, both the device dimensions and the supply voltage are reduced proportionally to maintain a nearly constant electric field, ensuring reliable operation while improving speed and reducing power consumption.
Ques: Why did constant voltage scaling remain more theoretical than practical?
Constant voltage scaling reduces transistor dimensions while keeping the supply voltage unchanged. Although this improves current drive and switching speed, it also significantly increases the internal electric field, resulting in severe short-channel effects, hot-carrier degradation, and oxide reliability problems. Consequently, constant voltage scaling is generally regarded as a theoretical scaling model, as modern semiconductor technologies reduce both device dimensions and operating voltage to maintain acceptable reliability.
Ques: What are short channel effects?
These are undesirable phenomena that arise when the channel length of a MOSFET becomes comparable to the depletion widths of the source and drain junctions. Under these conditions, the gate loses exclusive electrostatic control over the channel, allowing the drain and source electric fields to influence carrier transport. This results in effects such as threshold voltage roll-off, drain-induced barrier lowering (DIBL), punch-through, and increased subthreshold leakage current.
Ques: What is the difference between constant field and constant voltage scaling?
The primary difference lies in how the supply voltage is treated during device miniaturization. In constant field scaling, both the device dimensions and the operating voltage are reduced proportionally to maintain a constant electric field, improving reliability and reducing power consumption. In constant voltage scaling, the supply voltage remains unchanged while we reduce device dimensions which leads to increased electric fields, higher power density, and more pronounced short-channel effects. Due to this constant field scaling is considered more practical for modern CMOS technologies.
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